A flash memory array structure may be divided into a NAND type and a NOR type according to a logic structure thereof.
As shown in FIG. 1, a conventional NOR flash array has a single-transistor parallel structure. When an erasing operation is performed in a memory block, influenced by various elements such as process conditions and operation conditions, the erasing operation may lead partial cells to an over erasing state. As shown in FIG. 1, when reading a cell A, if the over erasing occurs to a cell B, a threshold voltage of the cell B is minus, thus causing a leakage, that is, a current of a bit line BL1 is an sum of a current of the cell A and a current of the cell B, which may cause a reading fault and a redundant power consumption. For an independent NOR flash, a complicated algorithm is usually introduced to solve an over erasing problem. For instance, an erasing verification is performed after the erasing operation. If there are over erased cells, a soft programming operation is performed to a full block until the threshold voltages thereof are programmed above zero using a low gate voltage. The verification and soft programming operation are repeated until a proportion of the over erased cells satisfies a requirement. The complicated algorithm increases a complexity of a peripheral control circuit.
Because the complicated algorithm mentioned above may greatly increase a complexity of a whole system, an introduction of the complicated algorithm is obviously not applicable for an eNOR flash (embedded-NOR flash). For the eNOR flash, a double-transistor parallel structure is usually used to solve the over erasing problem. As shown in FIG. 2, a MOSFET (metal-oxide-semiconductor field effect transistor) is disposed at a source region of each cell to control a selection of the cell. In this way, when reading a cell A, even the over erasing occurring to a cell B after the erasing operation, the leakage of cell B may not influence a current in a bit line BL1, because a transistor B′ connected with the cell B in series is off. In addition, this solution may simplify the peripheral control circuit. However, a storage density is greatly reduced because of the double-transistor cell structure.
Therefore, there is a need for a nonvolatile memory with a NOR type array structure which has advantages of a low power consumption, a high storage density and a simple peripheral control circuit.
In addition, a NAND type flash and a NOR type flash have complementary advantages and disadvantages because of their structure differences. For instance, the NAND type flash is applicable for a data storage with high density and mass capacity because of a compact array structure, while the NAND type flash has disadvantages of a low reading speed and a non-supporting code local execution. In contrast, the NOR type flash is applicable for a mass program storage because of a high reading speed and a code local-executed property, while the NOR type flash has disadvantages of a low storage density and a small capacity, and thus it is not applicable for the mass data storage.
Therefore, there is a need for a memory structure to realize the high speed reading, the code local execution and the mass data storage simultaneously.